In present-day communication systems, phase locked loops are often employed as part of the signal recovery scheme. Typically, a phase-locked loop may include a phase detector, a low pass filter and a voltage controlled oscillator. The controlled oscillator phase makes the signal recovery loop capable of locking onto or becoming synchronized with the carrier frequency of the incoming signal. As the phase between the carrier of the incoming signal and the output of the oscillator changes, indicating a change in carrier frequency in the incoming signal, the output of the phase detector changes proportionally, causing an adjustment of the oscillator output frequency to follow the change in the carrier frequency of the incoming signal and maintaining the signal recovery loop "locked" onto the carrier frequency of the incoming signal.
Unfortunately, because of the recovery mechanism inherent in its operation, the phase locked loop is susceptible to becoming stable in an anamolous locking mode in which the loop is locked onto a frequency other than the true carrier. In this condition, termed "sidelock," since the output frequency of the voltage controlled oscillator does not correspond to the carrier frequency of the incoming signal, demodulation of the incoming signal cannot be effected. This problem becomes especially severe in communication systems that employ PSK modulation techniques.
In a conventional signal recovery arrangement, the carrier may be recreated, for example, by first multiplying the received signal by a frequency multiplier corresponding to the number (M) of phases employed for the modulation of the (M-ary) PSK signal. The resulting signal is then coupled to a phase-locked loop, the voltage controlled oscillator of which produces a frequency M times the carrier f.sub.c. The output of the phase-locked loop is then equal of Mf.sub.c which, after division by M, can be employed for synchronous detection, i.e. signal recovery. Unfortunately, because of the characteristics of the input signal a plurality of sidebands spaced about either the carrier or another sideband by the modulation rate M of the PSK signal are produced. If the modulation rate is relatively small, e.g. binary or quaternary, compared to the frequency uncertainty of the received carrier, it may be effectively impossible to prevent sidelock. Namely, for binary PSK, false locks occur at one-half the symbol rate; for quaternary PSK, the false locks occur at one-fourth the symbol rate.
One proposal to circumvent this problem is described in the U.S. Pat. Nos. to Walker et al. 4,000,476 and Sanders et al. 4,077,016. Briefly, each patent describes a scheme wherein the conventional carrier recovery loop, including a lock detector, is provided with a sidelock or false lock detector which is tuned to a sideband of the true carrier center frequency f.sub.c. This sidelock detector cooperates with the conventional phase-locked loop to detect a sidelock condition and energize a lock inhibit circuit. The lock inhibit circuit prevents the phase-locked loop from remaining in the locked condition by activating or enabling a sweep generator to drive the reference oscillator away from the false lock sideband and hopefully toward the true carrier f.sub.c to be acquired. However, if a sidelock condition is again detected, the oscillator is again driven out of its locked condition; namely, the process is repeated until the voltage controlled oscillator is finally driven to the desired lock condition.
The schemes described in the above referenced patents are typically used in communication schemes where there is little filtering in the transmission path or which do not have a wide acquisition range. In satellite communication links, however, neither of these conditions is usually satisfied, so that the sidelock avoidance schemes described above are not effective.
More specifically, for narrowly filtered transmissions, the false lock condition can be as strong as true lock. Under this circumstance, what would normally be a fairly limited error voltage at the output of the phase locked loop becomes a very strong voltage, which effectively neutralizes the sweep voltage. Namely, as the sweep voltage generator is attempting to drive the voltage controlled oscillator away from the sideband in response to the output of the sidelock detector, the strong error voltage output of the phase locked loop is counteracting this action by driving it back toward the sidelock frequency. As a result, the loop is unable to extricate itself from the sidelock condition, so that signal recovery cannot be effected.
Another factor which makes the schemes described in the above-referenced literature unacceptable for satellite communication networks is the close channel spacing encountered coupled with a relatively wide acquisition range. Typically, a satellite communication network contains a large number of channels located close to one another in the frequency domain. In this type of communication environment, a scheme such as proposed by the patent to Sanders et al, for example, is ineffective, because the PSK modems for adjacent channels would interfere with the action of the false lock detector. Namely, the circuit which measures the energy at fixed frequency increments above and below the lock frequency (preferably twice the bit clock frequency) would also be acted on by closely spaced adjacent channels. For example, with the phase lock loop at true lock, a large amplitude adjacent channel could activate the false lock indicator and drive the loop away from true lock.